1. Field of the Invention
The embodiments of the invention generally relate ultra thin semiconductor devices and, more particularly, to a semiconductor structure and method of forming the structure that incorporates a first ultra-thin device having field effect transistors (FETs) with both front and back gates and a second ultra-thin device having FETs with only front gates.
2. Description of the Related Art
Ultra-thin silicon-on-insulator (UTSOI) field effect transistors (FETs) formed from wafers in which the active silicon layer is less 20 nm thick and therefore, fully depleted, show promise for incorporation into various semiconductor devices (e.g., logic circuits, memory cells, SRAM cells, analog devices, etc).
Such FETs can be formed either with or without back gates and the decision to form them with or without the back gates involves a trade-off between the need for threshold voltage (Vt) control and the need to avoid device performance degradation (i.e., reduction in speed) due to parasitic back gate capacitance. For example, devices formed with double-gated UTSOI FETs (i.e., FETs with both front and back gates) suffer from performance degradation, but exhibit optimal Vt control. Whereas, devices formed with single-gated UTSOI FETs (i.e., FETs with only a front gate) avoid performance degradation (i.e., maintain speed), but exhibit only marginal Vt control.
Consequently, devices that do not need fast switching speeds but require precise Vt control (e.g., static random access memory (SRAM) cells, analog devices designed for a specific function, etc.) may benefit from being formed with double-gated FETs. Contrarily, devices that require high performance (i.e., fast switching speeds) and need only marginal threshold voltage (Vt) control (e.g., logic circuits, analog devices designed for a specific function, etc.) may benefit from being formed with single-gated FETs. However, since it is often necessary to incorporate both types of devices on the same chip, there is a need in the art for a semiconductor structure that comprises both UTSOI FETs with front and back gates and UTSOI FETs with only front gates.